I've measured latency for 'lock cmpxchg' and 'mfence' instructions on Pentium 4 processor. Download After Burner Climax Pch. I've got following results: lock cmpxchg - 100 cycles mfence - 104 cycles So I conclude that they are nearly identical wrt consumed cycles. But is there some difference between them wrt system performance? Especially on modern multicore processors (Core 2 Duo, Core 2 Quad)? Is following assumption correct: Lock prefix affects bus/cache locking, so has impact on total system performance. And mfence has only local impact on current core.

X86 Serializing Instructions. Lego Instructions Online AMD64 Architecture Programmer’s Manual Volume 2: System Programming Publication No. Revision Date 24593 3. AMD64 Technology 24593—Rev. 3.23—May 2013 Trademarks. Membar #syncin SPARC,cpuidin X86, and isyncin PowerPC. Serial Number For I Mind Map 8 Key. Other Instructions Several other instructions, such as atomic read. The Intel 64 and IA-32 architectures define several serializing instructions. These instructions force the.

Or more practical: If I have 2 algorithms - one use lock prefix, and another use mfence. Other things being equal, what I must prefer?

Aluratek Software Update. Thanks for any advance Dmitriy V'jukov. Those two instructions do completely different things. You cannot use mfence instead of lock prefix. Description: Performs a serializing operation on all load and store instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes the MFENCE instruction is globally visible before any load or store instruction that follows the MFENCE instruction. The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any SFENCE and LFENCE instructions, and any serializing instructions (such as the CPUID instruction). Weakly ordered memory types can enable higher performance through such techniques as out-of-order issue, speculative reads, write-combining, and write-collapsing.

The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring ordering between routines that produce weakly-ordered results and routines that consume this data. It should be noted that processors are free to speculatively fetch and cache data from system memory regions that are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). The PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, the MFENCE instruction is not ordered with respect to PREFETCHh or any of the speculative fetching mechanisms (that is, data could be speculative loaded into the cache just before, during, or after the execution of an MFENCE instruction). I do not know what you are trying to do but I can tell you this — most I ever needed was SFENCE instruction when I was using non-temporal stores to copy data. That said, I haven't noticed any performance degradation from SFENCE.